(PDF) ATMEGA8 Datasheet – 8-bit Microcontroller
– 0 – 16MHz (ATmega8)
– 0 – 16MHz (ATmega8)
– 0 – 8MHz (ATmega8L)
– 0 – 8MHz (ATmega8L)
– 4.5V – 5.5V (ATmega8)
– 4.5V – 5.5V (ATmega8)
– 2.7V – 5.5V (ATmega8L)
– 2.7V – 5.5V (ATmega8L)
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Shorter pulses are not guaranteed to generate a reset.
38. Shorter pulses are not guaranteed to generate a reset.
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
generate a Reset.
generate a Reset.
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
ATmega8(L)
Arithmetic Logic
Unit – ALU
Status Register
The high-performance Atmel
®
AVR
®
ALU operates in direct connection with all the 32 general
purpose working registers. Within a single clock cycle, arithmetic operations between general
purpose registers or between a register and an immediate are executed. The ALU operations
are divided into three main categories – arithmetic, logical, and bit-functions. Some implementa-
tions of the architecture also provide a powerful multiplier supporting both signed/unsigned
multiplication and fractional format. For a detailed description,
see “Instruction Set Summary” on
page 311.
The Status Register contains information about the result of the most recently executed arithme-
tic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the
Instruction Set Reference.
This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.
The AVR Status Register – SREG – is defined as:
Bit
Read/Write
Initial Value
7
I
R/W
0
6
T
R/W
0
5
H
R/W
0
4
S
R/W
0
3
V
R/W
0
2
N
R/W
0
1
Z
R/W
0
0
C
R/W
0
SREG
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-
rupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the
Instruction Set Reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-
nation for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful
in BCD arithmetic. See the “Instruction
Set Description”
for detailed information.
• Bit 4 – S: Sign Bit, S = N
V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction
Set Description”
for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction
Set Description”
for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction
Set Description”
for detailed information.
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