Apple’s Pro Display XDR: custom Thunderbolt3 interface?

Massimiliano Greco

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Nov 14, 2019

6 min read

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When Intel introduced Thunderbolt 3 back in 2015, they released a family of controllers known as Alpine Ridge.
Alpine Ridge was able to support 2 DisplayPort 1.2 connections over a single TB3 link. This enabled Macs to drive the LG UltraFine 5K monitor.
In 2018 Intel added DisplayPort 1.4 support in TB3 with the new Titan Ridge controller, with all press outlets reporting a 2xDP1.4 capability.

Let’s clarify what a DisplayPort connection really is.
Each revision of the DisplayPort standard defines a new transmission mode with HBR2 mode used for DP1.2 and HBR3 for DP1.3/1.4.
Multiple lanes of data of a transmission mode can be grouped together to reach higher bandwidths, with a DisplayPort connector carrying 4 aggregated lanes of HBRx.

Looking at the table, it is easy to see that 8 HBR2 lanes (equivalent to 2 DP1.2 connections) can fit in a TB3 link since that would require an effective bandwidth of 34.56 Gbps (after accounting for encoding overhead) which is under the TB3 limit of 40Gbps.
Things get strange when one wants to verify the Titan Ridge claim (or at least the press claim) to be able to support 2 DisplayPort 1.4 connections.
This would require 8 lanes of HBR3 data that are equivalent to 51.84 Gbps effective bandwidth which is more than TB3’s maximum data rate of 40Gbps.

Intel’s own Titan Ridge datasheet lists support for HBR3 at a maximum of 4 lanes which makes much more sense as it requires a bandwidth which is under the 40Gbps TB3 limit.

So the myth of Titan Ridge being able to drive 8 HBR3 links is debunked, and the updated LG UltraFine 5K monitor with Titan Ridge continues to be driven by 8xHBR2 as 4xHBR3 is not enough to drive it (5120×2880 @60Hz 10bpc is 26.5Gbps which is only covered by 8xHBR2).

Problems start to arise once the new Pro Display XDR with its 6K resolution comes into play. In order to drive it (6016×3384 @60Hz 10 bpc), a bandwidth of 36.6 Gbps is needed which is not covered by any DisplayPort combination supported by Titan Ridge controllers.
I do not think Apple will resort to use DSC on this display (would be a decidedly un-Apple thing to do) so let’s imagine display stream compression is out of the equation.
[UPDATE: turns out Apple decided to use DSC, but this is only supported on Macs with AMD Navi GPU, so everything described in this post still applies to pre-Navi AMD GPU Macs and Intel iGPU only Macs. I guess image quality with DSC is pretty good 🙂 ]
6 lanes of HBR3 deliver a data rate of 38.88Gbps which would be enough to drive the XDR display (and compatible with the usual TB3 40Gbps limit). Except that no publicly available TB3 controller has this capability.

This got me thinking that since Intel recently open the TB3 standard, Apple could have built a custom Thunderbolt 3 controller with 6xHBR3 support.
The bandwidth needed could also be offered by a 9xHBR2 connection but this looks unlikely to be the case to me.
HDMI 2.1 as well is not fit for the job as it does not support the P3 gamut, so I don’t think Apple has implemented an HDMI 2.1 Alt Mode.
Obviously it is way too early for DisplayPort 2.0 (and no GPU supports it).

Both the freshly released 16″ MBP and the upcoming Mac Pro support the 6K display and a teardown should confirm or debunk my hypothesis.
I suspect there will be no Intel Titan Ridge controllers to be found on the logic boards (same things applies for the 6K display itself).
This could potentially be the first non-Intel TB3 controller available and it would only be fitting to Apple to be the first to do this since they rely so heavily on the technology.

[UPDATE 18 Nov 2019]
iFixit posted the 16″ MBP teardown.

Titan Ridge is indeed there, my theory was wrong.
But there might still be something custom, firmware specifically.
After speaking with someone more knowledgeable than me (last post here), there are 2 possible scenarios.

SCENARIO 1
We know Titan Ridge supports 8 lanes HBR2, this means that a configuration with 8 DP links from the GPU to the TB3 controller is possible (and is definitely present on Macs).
These 8 links are physically there and you use all of them when running in HBR2 mode and only 4 of them when using HBR3.
It is reasonable to assume that with some TB firmware changes one could drive up to 6xHBR3 lanes, since a total of 8 links connect GPU and TB3 controller anyways. Obviously 8xHBR3 is not possible due to the 40Gbps TB3 bandwidth limitation.

SCENARIO 2
This scenario is a bit more complex.
Looking at the Pro Display XDR specs, one can note that the USB ports on the back of the display are quoted as 2.0 speed when running at full resolution, but they are able to offer USB 3.1 Gen 1 speeds when the display is driven by an older Mac at a lower 5K resolution.
Dropping USB 3 as a result of running at 6K likely means that USB traffic is routed only through the dedicated USB 2.0 pins in USB-C ports (as mentioned here).
This would free up the 4 high-speed lanes of a USB-C connector to carry display data only. This makes sense since the display does not have any upstream TB3 ports and thus traffic in TB3 cable is only one-directional: exclusively from the system to the display.
All of this would allow the TB3 connection to work as a 80Gbps simplex link instead of a 40Gbps full duplex link (and incidentally this is what DP2.0 will do).
80 Gbps is a lot of bandwidth, easily coping with even a 8xHBR3 link which is more than enough to run the display at the full 6K resolution.

Both scenarios would require some low-level firmware work, but this sounds pretty achievable. Scenario 2 looks more likely as the USB 2 speed limitation seems to hint in that direction.
Another point supporting the theory that 8HBR2/4HBR3 is not a hard limit in Titan Ridge is the fact that Dell’s WD19TB dock seems to support 5 lanes of HBR3 as reported in the manual.
This would suggest that either Titan Ridge datasheet has a typo in it or if you really want to push for more display bandwidth you can play around and get more out of Titan Ridge (or both).

It will be super interesting, once the 6K display gets in the hands of people, to try and see if it is possible to somehow obtain data from the TB3 controller or the GPU about how many HBR3 lanes are used and how the TB3 link itself is being used.

[UPDATE 19 Apr 2020]

Thanks to a commenter who pointed this forum, I have now understood what is going on.
TB3 signals can allocate DisplayPort bandwidth exctly as needed, without having to use full HBR lanes. This means that given the 36.6 Gbps needed to drive the Pro Display XDR, the TB3 link can allocate the equivalent 5.6 HBR3 lanes (each lane can give you 6.48 Gbps effective bandwidth) to DisplayPort traffic and leave the rest for PCIe traffic.
Keeping in mind the total link budget for TB3 of 40 Gbps, that would leave 3.4 Gbps to PCIe data, which will not allow a full USB 3.0 (or 3.2 Gen 1) connection of 5 Gbps.
I would guess that in order to not confuse users with a not-quite 3.0 USB connection, they just chose to advertise the USB ports as 2.0 for simplicity.